Cerebras Wafer-Scale Defect-Tolerance Simulator

An interactive systems view of how a wafer-scale chip stays operational when faults appear. Use the controls to stress defects, links, and remap budget and watch packet flow adapt.

Healthy tile

Repaired / remapped tile

Defective tile

I/O edge

Active path

Reliability simulation runs 40 randomized maps with current sliders and remap policy.

3D controls

Display controls

Demo mode (hide long notes)

Auto-rotate 3D scene Show defect cluster outlines

Manufacturing tile defects:

Inter-tile link defects:

Spare-core remap budget (percent):

Enable cluster remap for small defect groups Loop packet pulse for continuous demo capture Show mesh links

Packet pulse speed:

Lower number = faster motion.

Ready

Reliability run visual

Success: — Fail: — Avg route: —

Demo script

Demo flow: Generate chip map → pulse packet route.
Demo mode: enable Loop packet pulse and tune speed while narrating.
Readout: status bar and KPIs update after packet path pulses.
What to watch: repaired/active path, blocked routes, and cluster repair behavior under pressure.

Legend

Repair marker: clusters assigned spare tiles are shown in the remap color.
Mesh markers: cluster outlines and failed links are drawn when enabled.
Path marker: the highlighted route is the current packet walk through healthy nodes.

Healthy tiles —

Repaired tiles —

Faulty links —

Routed packet —

Utilization —

Remap utilization —

Reliability (40 runs) —

Defect cluster outline

Mesh link overlay

Bad fabric link

What this depicts

Each tile is a simplified compute/fabric region with local SRAM and packet-style dataflow behavior.
Modeled as one continuous wafer-scale die, with faults and link failures injected per control settings.
Data moves only across healthy neighboring tiles and healthy links; failed links force reroutes.
Remap uses local repair clusters + criticality-aware scoring, plus a spare tile budget.
Accuracy note: this is a concept-level simulator, not a full power/timing/clock-domain model.
Built for real-time interaction and systems-level understanding. Exact architecture details are in source links.

Source notes (from cited materials)

Wafer-scale size: WSE-3 is reported as ~46,225 mm² in the defect-tolerance framing, and ~46,250 mm² in CS-3 product materials, versus a H100-size area in the ~800 mm² class.
Core size argument: WSE-3 core area is cited around ~0.05 mm² (about 100x smaller than an H100-style ~6.2 mm² SM core).
Yield comparison framing (blog): one 46,225 mm² wafer-scale chip per 300mm wafer vs roughly ~72 H100-size chips at around 814 mm² in their walkthrough.
Manufacturing geometry context: conventional wafers are typically diced into many reticle-sized dies; WSE uses field stitching and keeps one contiguous active wafer-scale array.
Defect tolerance outcome: the model reflects small fault domains + local rerouting + limited spare capacity, then evaluates path completion under repeated randomized runs.
IEEE 2021 context note: WSE-2-era papers describe stitched 525 mm² reticles and a low (roughly 1%) spare PE reserve with local rerouting at PE granularity; this simulator maps that idea at tile granularity, not reticle scale.
WSI fabric behavior (IEEE Micro): shorter on-chip links are modeled as local inter-tile links; failed links can block mesh paths and force alternate local routing in this model.
Cerebras WSE-3 reporting: ~93% usable silicon area and ~900,000 active cores (from the public WSE-3 discussion).
Yield framing in this page is a simplification, meant to show concept-level effects of defect clusters, links, and remap budget.

Based on public Cerebras defect-tolerance material

Cerebras blog IEEE Micro paper WSI report Further details